atomic.h

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00001 /*
00002  * Copyright (C) 2005, 2007  Internet Systems Consortium, Inc. ("ISC")
00003  *
00004  * Permission to use, copy, modify, and/or distribute this software for any
00005  * purpose with or without fee is hereby granted, provided that the above
00006  * copyright notice and this permission notice appear in all copies.
00007  *
00008  * THE SOFTWARE IS PROVIDED "AS IS" AND ISC DISCLAIMS ALL WARRANTIES WITH
00009  * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
00010  * AND FITNESS.  IN NO EVENT SHALL ISC BE LIABLE FOR ANY SPECIAL, DIRECT,
00011  * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
00012  * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
00013  * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
00014  * PERFORMANCE OF THIS SOFTWARE.
00015  */
00016 
00017 /* $Id: atomic.h,v 1.3 2007/06/19 23:47:18 tbox Exp $ */
00018 
00019 #ifndef ISC_ATOMIC_H
00020 #define ISC_ATOMIC_H 1
00021 
00022 #include <isc/platform.h>
00023 #include <isc/types.h>
00024 
00025 #ifdef ISC_PLATFORM_USEGCCASM
00026 /*
00027  * This routine atomically increments the value stored in 'p' by 'val', and
00028  * returns the previous value.
00029  */
00030 static inline isc_int32_t
00031 isc_atomic_xadd(isc_int32_t *p, int val) {
00032         isc_int32_t orig;
00033 
00034         /* add is a cheat, since MIPS has no mov instruction */
00035         __asm__ volatile (
00036             "1:"
00037             "ll $3, %1\n"
00038             "add %0, $0, $3\n"
00039             "add $3, $3, %2\n"
00040             "sc $3, %1\n"
00041             "beq $3, 0, 1b"
00042             : "=&r"(orig)
00043             : "m"(*p), "r"(val)
00044             : "memory", "$3"
00045                 );
00046 
00047         return (orig);
00048 }
00049 
00050 /*
00051  * This routine atomically stores the value 'val' in 'p'.
00052  */
00053 static inline void
00054 isc_atomic_store(isc_int32_t *p, isc_int32_t val) {
00055         __asm__ volatile (
00056             "1:"
00057             "ll $3, %0\n"
00058             "add $3, $0, %1\n"
00059             "sc $3, %0\n"
00060             "beq $3, 0, 1b"
00061             :
00062             : "m"(*p), "r"(val)
00063             : "memory", "$3"
00064                 );
00065 }
00066 
00067 /*
00068  * This routine atomically replaces the value in 'p' with 'val', if the
00069  * original value is equal to 'cmpval'.  The original value is returned in any
00070  * case.
00071  */
00072 static inline isc_int32_t
00073 isc_atomic_cmpxchg(isc_int32_t *p, int cmpval, int val) {
00074         isc_int32_t orig;
00075 
00076         __asm__ volatile(
00077             "1:"
00078             "ll $3, %1\n"
00079             "add %0, $0, $3\n"
00080             "bne $3, %2, 2f\n"
00081             "add $3, $0, %3\n"
00082             "sc $3, %1\n"
00083             "beq $3, 0, 1b\n"
00084             "2:"
00085             : "=&r"(orig)
00086             : "m"(*p), "r"(cmpval), "r"(val)
00087             : "memory", "$3"
00088                 );
00089 
00090         return (orig);
00091 }
00092 
00093 #else /* !ISC_PLATFORM_USEGCCASM */
00094 
00095 #error "unsupported compiler.  disable atomic ops by --disable-atomic"
00096 
00097 #endif
00098 #endif /* ISC_ATOMIC_H */

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