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00019 #ifndef ISC_ATOMIC_H
00020 #define ISC_ATOMIC_H 1
00021
00022 #include <isc/platform.h>
00023 #include <isc/types.h>
00024
00025 #ifdef ISC_PLATFORM_USEGCCASM
00026
00027
00028
00029
00030 static inline isc_int32_t
00031 isc_atomic_xadd(isc_int32_t *p, int val) {
00032 isc_int32_t orig;
00033
00034
00035 __asm__ volatile (
00036 "1:"
00037 "ll $3, %1\n"
00038 "add %0, $0, $3\n"
00039 "add $3, $3, %2\n"
00040 "sc $3, %1\n"
00041 "beq $3, 0, 1b"
00042 : "=&r"(orig)
00043 : "m"(*p), "r"(val)
00044 : "memory", "$3"
00045 );
00046
00047 return (orig);
00048 }
00049
00050
00051
00052
00053 static inline void
00054 isc_atomic_store(isc_int32_t *p, isc_int32_t val) {
00055 __asm__ volatile (
00056 "1:"
00057 "ll $3, %0\n"
00058 "add $3, $0, %1\n"
00059 "sc $3, %0\n"
00060 "beq $3, 0, 1b"
00061 :
00062 : "m"(*p), "r"(val)
00063 : "memory", "$3"
00064 );
00065 }
00066
00067
00068
00069
00070
00071
00072 static inline isc_int32_t
00073 isc_atomic_cmpxchg(isc_int32_t *p, int cmpval, int val) {
00074 isc_int32_t orig;
00075
00076 __asm__ volatile(
00077 "1:"
00078 "ll $3, %1\n"
00079 "add %0, $0, $3\n"
00080 "bne $3, %2, 2f\n"
00081 "add $3, $0, %3\n"
00082 "sc $3, %1\n"
00083 "beq $3, 0, 1b\n"
00084 "2:"
00085 : "=&r"(orig)
00086 : "m"(*p), "r"(cmpval), "r"(val)
00087 : "memory", "$3"
00088 );
00089
00090 return (orig);
00091 }
00092
00093 #else
00094
00095 #error "unsupported compiler. disable atomic ops by --disable-atomic"
00096
00097 #endif
00098 #endif